Circuit emulation is a common and integral part of the process of designing and manufacturing integrated circuits (ICs), which are often mass produced, sold, and incorporated into systems in the form of semiconductor chips. As an illustrative example, an emulation system or simulator may be a hardware device that can be programmed to simulate a newly designed circuit. The programmed emulation system may then be used to verify the operational behavior of the circuit to see if the circuit properly functions for its intended purposes without errors. The signals flow internally within the emulated circuit and the signal inputs and outputs of the emulated circuit may be monitored for the purpose of verifying operational behaviors, identifying errors that may occur, and correcting design or functional flaws.
An IC designer may use an emulation system at various stages of a design process to verify that the IC will function and behave as expected. As an example, a designer may develop a “test bench” for an emulation system by programming it to simulate an IC device under test (DUT). The system may indicate how the various internal or external signals of the DUT change states over time and allow the monitoring of these various signals and the behaviors of the DUT during the emulation, such as how the DUT responds to various input signals. As an example, the system may generates a “dump file” containing waveform data representing the time-varying behaviors of monitored signals. The designer may then use various examination or debugging tools to analyze the dump file and determine whether the DUT behaved as expected.
As an illustrative example, FIG. 1 illustrates a prior-art emulation system or emulator 10 including a set of sectional circuit boards 12 each holding an array of programmable gate arrays (FPGAs) 14, each of which may be programmed to emulate the logic of a large number of interconnected logic gates, flip-flops, registers, etc. Each FPGA 14 may have many I/O (input/output) terminals, and some of those I/O terminals are linked to the I/O terminals of other FPGAs 14 on the same circuit board 12 so that the FPGAs can communicate with one another. In one embodiment, these sectional circuit boards 12 may reside in slots on a main circuit board (or motherboard) 15, which may include a backplane for interconnecting I/O terminals of FPGAs 14 residing on different circuit boards 12 so that they too can communicate with one another.
Coupled with motherboard 15 through an I/O interface 17, workstation 16 may process the user's description of a DUT to program FPGAs 14 to emulate DUT logic and transmits those instructions to programming inputs of FPGA 14. I/O interface 17 may be an I/O interface card 17 that may be installed in workstation 16, such as in a slot of the PCI bus of workstation 16. Each I/O interface card 17 may transmit signals to and receive signals from resources mounted on motherboard 15 via signal paths motherboard 15 provides.
In addition to logic, FPGAs 14 can emulate ICs including large standardized components such as embedded computer processors and memories. The ICs and large standardized components can be emulated by processors or memory ICs mounted on “resource boards” 18 that may also be installed in slots of motherboard 15. Backplane wiring on motherboard 15 may link terminals of the devices mounted on resource boards 18 to I/O terminals of various FPGAs 14 mounted on FPGA boards 12.
An IC is often designed to be installed on a circuit board of an external system so that it can communicate with other devices within that system. When emulator 10 acts as an in-circuit emulation (ICE) system, the emulator may include an external system interface circuit 22 providing signal paths between I/O terminals of FPGAs 14 and a socket of the external system 24 of the type in which the IC being emulated will eventually reside. A cable 27 interconnects interface 22 with external system 24 and typically includes a connector that fits into the IC socket.
Emulation system 10 may also include pattern generation and data acquisition circuits 26 on motherboard 15. Pattern generation and data acquisition circuits 26 may be coupled with some of the signals paths on the motherboard or to I/O terminals of FPGAs 14 and may supply input signals to the FPGAs and monitor selected FPGA output signals during the emulation process to acquire “probe data” representing the behavior of the DUT output signals.
As another illustrative example, FIG. 2 illustrates a prior-art emulator architecture 20. Referring to FIG. 2, resource cards 28 may be mounted in slots of a workstation 33 and may emulate some portions of a DUT while workstation 33 emulates other portions of the DUT. Each card 28 may include an array of interconnected FPGAs 14 and may include other resources 30 such as memories linked to I/O terminals of FPGAs 14. An I/O interface circuit 32 in each card 28 may include I/O terminals connected to many I/O terminals of FPGAs 14. Workstation 33 may send instructions via its communication bus to the I/O interface circuit 32 on each card 28.
When the complexity of an emulated circuit increases, it may become necessary to use or combine multiple circuit boards, such as circuit board 12, main circuit board or motherboard 15, and resource board 18 in FIG. 1. Circuit boards may be stacked vertically and communicate using a shared communication bus. However, the limited number of channels or signal paths available on the shared communication bus may limit the number of signals that can be exchanged or monitored at the same time. For example, FIG. 3 is a diagram illustrative of a multiple-circuit-board system in the prior art. The circuit boards 60A, 60B, 60C, and 60D communicate with each other using a shared communication bus 62, which provides a limited number of channels or signal paths. As the complexity of a simulated circuit increases, so does the number of signals to be exchanged or monitored. The limitation on the number of channels or signal paths may limit the number of input signals to and output signals from the simulated circuit and may limit a designer's ability to effectively monitor the operations of the simulated circuit in certain emulation scenarios.